This invention relates to using an immediate operand in a computer instruction.
Integrated processor design generally involves a tradeoff in the size of the logic area devoted to processor logic and the area devoted to memory. Therefore the overall width (i.e., the number of bits) of a particular processor""s instructions is limited by the available width of the instruction memory. The individual bits of a processor instruction are interpreted by decode logic. A portion of an instruction is used to control processor operations (the xe2x80x9ccontrol fieldxe2x80x9d) and a portion of the instruction is used as an address of an operand (the xe2x80x9caddress fieldxe2x80x9d). For example, an address field may contain an address of a register containing an operand. An alternative way of providing an operand for processing is the use of an xe2x80x9cimmediate operandxe2x80x9d, i.e., using the address field of an instruction to store the actual operand. Therefore, the length of an immediate operand is limited by the width of the address field of an instruction.